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| OKI Semiconductor MD56V62160E 4-Bank x 1,048,576-Word x 16-Bit SYNCHRONOUS DYNAMIC RAM FEDD56V62160E-01 Issue Date: Feb. 4, 2002 DESCRIPTION The MD56V62160E is a 4-Bank x 1,048,576-word x 16-bit Synchronous dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES * Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell * 4-Bank x 1,048,576-word x 16-bit configuration * Single 3.3 V power supply, 0.3 V tolerance * Input : LVTTL compatible * Output : LVTTL compatible * Refresh : 4096 cycles/64 ms * Programmable data transfer mode - CAS Latency (1, 2, 3) - Burst Length (1, 2, 4, 8, Full Page) - Data scramble (sequential, interleave) * CBR auto-refresh, Self-refresh capability * Packages: 54-pin 400 mil plastic TSOP (TypeII) (TSOP(2)54-P-400-0.80-K)(Product: MD56V62160E-XXTA) xx indicates speed rank. PRODUCT FAMILY Family Max. Frequency 143 MHz 100 MHz Access Time (Max.) tAC2 6 ns 6 ns tAC3 6 ns 6 ns MD56V62160E-7 MD56V62160E-10 1/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 VCCQ 3 DQ2 4 DQ3 5 VSSQ 6 DQ4 7 DQ5 8 VCCQ 9 DQ6 10 DQ7 11 VSSQ 12 DQ8 13 VCC 14 LDQM 15 WE 16 CAS 17 RAS 18 CS 19 A13 20 A12 21 A10 22 A0 23 A1 24 A2 25 A3 26 VCC 27 54 VSS 53 DQ16 52 VSSQ 51 DQ15 50 DQ14 49 VCCQ 48 DQ13 47 DQ12 46 VSSQ 45 DQ11 44 DQ10 43 VCCQ 42 DQ9 41 VSS 40 NC 39 UDQM 38 CLK 37 CKE 36 NC 35 A11 34 A9 33 A8 32 A7 31 A6 30 A5 29 A4 28 VSS 54-Pin Plastic TSOP(II) (K Type) Pin Name CLK CS CKE A0-A10 A11 RAS CAS WE Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Pin Name UDQM, LDQM DQi VCC VSS VCCQ VSSQ NC Function Data Input/ Output Mask Data Input/ Output Power Supply (3.3 V) Ground (0 V) Data Output Power Supply (3.3 V) Data Output Ground (0 V) No Connection Note : The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E PIN DESCRIPTION CLK CS Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Row & column multiplexed. Row address : RA0 - RA11 Column Address : CA0 - CA7 Slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. CKE Address A13, A12 (BA0, BA1) RAS CAS WE UDQM, LDQM DQi Functionality depends on the combination. For details, see the function truth table. Masks the read data of two clocks later when UDQM and LDQM are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when UDQM and LDQM are set "H" at the "H" edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte. Data inputs/outputs are multiplexed on the same pin. 3/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E BLOCK DIAGRAM CKE CLK CS RAS CAS WE UDQM LDQM Progra-m ing Register Latency & Burst Controller I/O Controller Timing Register Bank Controller A13, A12 Internal Col. Address Counter A0 - A11 Input Data Register 16 88 Column Address Buffers 8 Column Decoders Input Buffers 16 Sense Amplifiers Internal Row Address Counter 16 Read Data Register 16 Output Buffers 16 DQ1 DQ16 12 Row Decoders Row Decoders Word Drivers Word Drivers 16Mb Memory Cells 16Mb Memory Cells 12 12 Row Address Buffers Sense Amplifiers Column Decoders 8 Column Decoders Sense Amplifiers Row 12 Decoders Row 12 Decoders Word Drivers Word Drivers 16Mb Memory Cells 16Mb Memory Cells Sense Amplifiers 8 Column Decoders 4/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS VCC Supply Voltage Storage Temperature Power Dissipation Short Circuit Output Current Operating Temperature Symbol VIN, VOUT VCC , VCCQ Tstg PD* IOS Topr Value -0.5 to VCC+ 0.5 -0.5 to 4.6 -55 to 150 1000 50 0 to 70 Unit V V C mW mA C *: Ta = 25C Recommended Operating Conditions (Voltages referenced to VSS = 0 V) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC, VCCQ VIH VIL Min. 3.0 2.0 -0.3 Typ. 3.3 Max. 3.6 VCC + 0.3 0.8 Unit V V V Pin Capacitance (Vbias = 1.4 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (CLK) Input Capacitance (RAS, CAS, WE, CS, CKE, UDQM, LDQM, A0 - A13) Input/Output Capacitance (DQ1 - DQ16) COUT 4 6.5 pF CIN 2.5 5 pF Symbol CCLK Min. 2.5 Max. 4 Unit pF 5/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E DC Characteristics MD56V62160 Condition Parameter Symbol E-7 E-10 Max. 0.4 10 10 Min. 2.4 -10 -10 Max. 0.4 10 10 Unit Note Bank Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current VOH VOL ILI ILO CKE Others IOH = -2.0mA IOL = 2.0mA Min. 2.4 -10 -10 V V A A ICC1 Average Power Supply Current (Operating) tCC = Min. One Bank CKE VIH tRC = Min. Active No Burst tCC = Min. tRC = Min. tRRD = Min. No Burst 85 70 mA 1,2 Both ICC1D Banks Active CKE VIH 135 115 mA 1,2 Power Supply Current (Standby) Average Power Supply Current (Clock Suspension) Average Power Supply Current (Active Standby) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power Down) Both ICC2 Banks CKE VIH tCC = Min. Precharge Both ICC3S Banks Active 30 30 mA 3 CKE VIL tCC = Min. 3 3 mA 2 ICC3 One Bank CKE VIH tCC = Min. Active 40 30 mA 3 Both ICC4 Banks Active ICC5 CKE VIH tCC = Min. 110 90 mA 1,2 One Bank t = Min. CKE VIH CC Active tRC = Min. 135 115 mA 2 Both ICC6 Banks CKE VIL Precharge tCC = Min. 2 2 mA Both ICC7 Banks CKE VIL tCC = Min. Precharge 2 2 mA Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. DC 6/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Mode Set Address Keys Single Write CAS Latency Burst Type Burst Length A9 0 1 BRSW Normal Single Write A6 A5 A4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CL Reserved 1 2 3 Reserved Reserved Reserved Reserved A3 0 1 BT Sequential A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8 Interleave Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Notes: A7, A8, A10, A11, A12 and A13 should stay "L" during mode set cycle. MD56V62160E supports two methods of Power on Sequence. POWER ON SEQUENCE 1 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. POWER ON SEQUENCE 2 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Enter the mode register setting command. 5. Apply a CBR auto-refresh eight or more times. 7/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E AC Characteristics (1/2) Note1, 2 MD56V62160 Parameter Symbol Min. E-7 Max. 6 6 17 6 100,000 64 1 1 2 0 Min. 10 10 20 3 3 3 1 1 3 70 20 50 20 10 20 tSI +1CLK 1 1 2 0 E-10 Max. 6 6 17 6 100,000 64 Unit Note CL = 3 Clock Cycle Time CL = 2 CL = 1 CL = 3 Access Time from Clock CL = 2 CL = 1 Clock High Pulse Time Clock Low Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock Random Read or Write Cycle Time RAS Precharge Time RAS Pulse Width RAS to CAS Delay Time Write Recovery Time RAS to CAS Bank Active Delay Time Refresh Time Power-down Exit setup Time CAS to CAS Delay Time (Min.) Clock Disable Time from CKE Data Output High Impedance Time from UDQM, LDQM Dada Input Mask Time from UDQM, LDQM tCC3 tCC2 tCC1 tAC3 tAC2 tCC1 tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tRRD tREF tRDE lCCD lCKE lDOZ lDOD 7 10 20 2 2 1.5 0.8 1 2 69 20 49 20 8 14 tSI +1CLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns Cycle Cycle Cycle Cycle 3, 4 3, 4 3, 4 4 4 3 8/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E AC Characteristics (2/2) Note1, 2 MD56V62160 Parameter Symbol Min. Data Input Mask Time from Write Command Data Output High Impedance Time from Precharge Command Active Command Input Time from Mode Register Set Command Input (Min.) Write Command Input Time from Output lDWD lROH 0 CL E-7 Max. Min. 0 CL E-10 Max. Cycle Cycle Unit Note lMRD 2 2 Cycle lOWD 2 2 Cycle Notes: 1. AC measurements assume that tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. The input signal conditions are below. VIH = 2.4 V, VIL = 0.4 V 3. Output load. Z = 50 Output 50 pF (External Load) 4. The access time is defined at 1.4 V. 5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. 9/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E TIMING CHART Read & Write Cycle (Same Bank) @CAS Latency = 2, Burst Length = 4 0 CLK tRC CKE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CS tRP RAS tRCD CAS ADDR Ra Ca0 Rb Cb0 A12, A13 A10 Ra tOH Rb DQ tAC WE Qa0 Qa1 Qa2 Qa3 tOH Db0 Db1 Db2 Db3 UDQM, LDQM Row Active Read Command Row Active Write Command Precharge Command Precharge Command 10/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency = 2, Burst Length = 4 0 CLK tCC CKE tCL High 1 2 3 4 tCH 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CS tHI RAS tSI CAS tSI ADDR Ra tHI A12. A13 BS BS tSI Ca tHI BS BS BS tSI Cb Cc tHI ICCD tSI A10 Ra tAC tHI tOHZ Qa tOLZ tOH lOWD Db tSI tHI Qc DQ WE tSI UDQM, LDQM Row Active Read Command Write Command Precharge Command Read Command 11/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E *Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, UDQM and LDQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A12 and A13. A11 0 0 1 1 A12 0 1 0 1 Active, read or write Bank A Bank B Bank C Bank D 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 0 1 0 1 0 1 0 1 A12 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 Operation After the end of burst, bank A holds the idle status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. After the end of burst, bank C holds the idle status. After the end of burst, bank C is precharged automatically. After the end of burst, bank D holds the idle status. After the end of burst, bank D is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 0 0 0 0 1 A12 0 0 1 1 X A13 0 1 0 1 X Operation Bank A is precharged. Bank B is precharged. Bank C is precharged. Bank D is precharged. All banks are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1CLK+ tOHZ ) after UDQM, LDQM entry. 12/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Page Read & Write Cycle (Same Bank) @CAS Latency = 2, Burst Length = 4 0 CLK High CKE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CS Bank A Active RAS CAS ICCD ADDR Ca0 Cb0 Cc0 Cd0 A12, A13 A10 DQ Qa0 Qa1 Qb0 Qb1 lOWD Dc0 Dc1 Dd0 tWR Note 2 WE Note 1 UDQM, LDQM Read Command Read Command Write Command Precharge Command Write Command *Notes: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Burst Read & Single Write Cycle (Same Bank) @CAS Latency = 2, Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE CS RAS tRCD CAS ADDR Ra Ca0 Cb0 Cc0 A12, A13 BS BS BS BS A10 Ra tOH Note 1 DQ tAC WE Qa0 Qa1 Qa2 Qa3 tOH Db0 Qc0 Qc1 Qc2 Qc3 UDQM, LDQM Row Active Read Command Write Command Read Command Precharge Command *Note: 1. If you set A9 to high during mode register set cycle, the write burst length is set to 1. 14/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS tRRD CAS ADDR Ra Rb Ca Cb A12, A13 A10 Ra Rb WE CAS Latency=1 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start Db0 Db1 Db2 Db3 UDQM, LDQM CAS Latency=2 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start Db0 Db1 Db2 Db3 UDQM, LDQM CAS Latency=3 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start Db0 Db1 Db2 Db3 tWR UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) A Bank Read with Auto Precharge B Bank Write with Auto Precharge B Bank Precharge Start Point 15/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Bank Interleave Random Row Read Cycle @CAS Latency = 2, Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS tRC RAS tRRD CAS ADDR RAa CAa RBb CBb RAc CAc A12, A13 A10 RAa RBb RAc DQ QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 WE UDQM, LDQM Row Active Read Command Read Command Row Active (A-Bank) (B-Bank) (A-Bank) (B-Bank) Read Command Row Active Precharge Command (A-Bank) (A-Bank) Precharge Command (A-Bank) (B-Bank) 16/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Bank Interleave Random Row Write Cycle @CAS Latency = 2, Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc A12, A13 A10 RAa RBb RAc DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Precharge Command (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) Row Active (A-Bank) 17/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Bank Interleave Page Read Cycle @CAS Latency = 2, Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE Note 1 High CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd CAe A12, A13 A10 RAa RBb DQ WE QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 IROH UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Read Command (A-Bank) *Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 18/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Bank Interleave Page Write Cycle @CAS Latency = 2, Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd A12, A13 A10 RAa RBb DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Write Command (B-Bank) Precharge Command (Both Bank) Write Command (A-Bank) Write Command (A-Bank) 19/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Bank Interleave Random Row Read/Write Cycle @CAS Latency = 2, Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc A12, A13 A10 RAa RBb RAc DQ QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 WE UDQM, LDQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Row Active (A-Bank) 20/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Bank Interleave Page Read/Write Cycle @CAS Latency = 2, Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 High CKE CS RAS CAS ADDR CAa0 CBb0 CAc0 A12, A13 A10 DQ QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 WE UDQM, LDQM Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 21/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length = 4 0 CLK Note 1 CKE Note 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CS RAS CAS ADDR Ra Ca Cb Cc A12, A13 A10 Ra DQ Qa0 Qa1 Note 2 Qa2 tOHZ Qb0 Qb1 tOHZ Dc0 Dc2 Note 3 WE UDQM, LDQM Row Active Read Command Read DQM CLOCK Suspension Read Command Read DQM Write DQM Write Command Write DQM CLOCK Suspension *Note: 1. 2. 3. 4. 5. When Clock Suspension is asserted, the next clock cycle is ignored. When UDQM and LDQM are asserted, the read data after two clock cycles is masked. When UDQM and LDQM are asserted, the write data in the same clock cycle is masked. When LDQM is set High, the input/output data of DQ1 - DQ8 is masked. When UDQM is set High, the input/output data of DQ9 - DQ16 is masked. 22/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Read to Write Cycle (Same Bank) @CAS Latency = 2, Burst Length = 4 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE CS Note 1 RAS tRCD CAS ADDR Ra Ca0 Cb0 A12, A13 A10 Ra DQ Da0 Db0 Db1 Db2 Db3 tWR WE UDQM, LDQM Row Active Read Command Write Command Precharge Command *Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. UDQM, LDQM must be high at least 3 clocks prior to the write command. 23/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Read Interruption by Precharge Command @Burst Length = 8 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 High CKE CS RAS CAS ADDR Ra Ca A12, A13 A10 Ra WE CAS Latency=1 DQ Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 lROH UDQM, LDQM CAS Latency=2 DQ Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 lROH UDQM, LDQM CAS Latency=3 DQ Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 lROH UDQM, LDQM Row Active Read Command Precharge Command *Note: 1. If row precharge is asserted before a burst read ends, then the read data will not output after lROH equals CAS latency. 24/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Burst Stop Command @Burst Length = 8 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 High CKE CS RAS CAS ADDR Ca Cb A12, A13 A10 WE CAS Latency = 1 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 UDQM, LDQM CAS Latency = 2 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 UDQM, LDQM CAS Latency = 3 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 UDQM, LDQM Read Command Burst Stop Command Write Command Burst Stop Command 25/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Power Down Mode @CAS Latency = 2, Burst Length = 4 0 CLK tSI CKE tREF (min.) CS Note 1 tPDE Note 2 t tSI SI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAS CAS ADDR Ra Ca A12, A13 A10 Ra DQ WE Qa0 Qa1 Qa2 UDQM, LDQM Power-down Entry Row Active Clock Power-down Exit Suspension Entry Read Command Clock Suspension Exit Precharge Command *Note: 1. When both banks are in precharge state, and if CKE is set low, then the MD56V62160E enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1CLK). 26/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Self Refresh Cycle 0 CLK tRC CKE tSI CS 1 2 RAS CAS ADDR Ra A12, A13 BS A10 Ra DQ WE Hi-Z UDQM, LDQM Self Refresh Entry Self Refresh Exit Row Active 27/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E Mode Register Set Cycle 0 CLK 1 2 3 4 5 6 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 CKE High High CS lMRD RAS tRC CAS ADDR Key Ra DQ Hi - Z Hi - Z WE UDQM, LDQM MRS New Command Auto Refresh Auto Refresh 28/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E FUNCTION TRUTH TABLE (Table 1) (1/2) Current 1 State Idle CS H L L L L L L L RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H BA X X BA BA BA BA X L X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X BA BA X BA X X X BA BA ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 NOP NOP ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Action Auto-Refresh or Self-Refresh 5 Mode Register Write NOP NOP Read Write ILLEGAL 2 Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Term Burst --> Row Active Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Term Burst --> Row Active Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 ILLEGAL 2 Term Burst, execute Row Precharge 3 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 Row Active H L L L L L L Read H L L L L L L L Write H L L L L L L L Read with Auto Precharge H L L L L L L Write with Auto Precharge H L L L 29/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 Write with Auto Precharge Precharge CS L L L H L L L L L L RAS H L L X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L CAS L H L X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X WE L X X X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BA X BA X X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X RA, A10 X X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X ILLEGAL ILLEGAL 2 ILLEGAL NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL NOP NOP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 Action Write Recovery H L L L L L L Row Active H L L L L L L ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Refresh H L L L L Mode Register Access H L L L L ABBREVIATIONS RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge NOP = No OPeration command Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 30/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh 6 H L L L L L L Power Down 6 CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L CS X H L L L L X X H L L L L X X H L L L L L L X X X X X RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X WE X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL 6 NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension H L L L L L L All Banks Idle 7 (ABI) H H H H H H H H L Any State Other than Listed Above H H L L *Notes : 6. If the minimum set-up time tPDE is satisfied when CKE transition from "L" to "H", CKE operates asynchronously so that a command can be input in the same internal clock cycle. 7. Power-down and self-refresh can be entered only when all the banks are in an idle state. 31/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E PACKAGE DIMENSIONS (Unit: mm) TSOP(2)54-P-400-0.80-K Mirror finish 5 Notes for Mounting the Surface Mount Type Package Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 0.55 TYP. 1/Aug. 14, 1997 The QFP is a surface mount type package, which is very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 32/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E REVISION HISTORY Document No. FEDD56V62160E-01 Date Feb. 4, 2002 Page Previous Current Edition Edition - - First edition Description 33/34 FEDD56V62160E-01 OKI Semiconductor MD56V62160E NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 34/34 |
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